Multistage decoding

ABSTRACT

An improved row decoding technique for use in a static RAM. Three stages of row decoders are utilized to further decode partially decoded row address signals and combine the decoded signals with a column address signal to enable selected rows of the memory array. To optimize decoding speed, each stage comprises gates which receive only two inputs from the prior stage and the stages are arranged to allow for sharing of signals between adjacent decoders.

BACKGROUND OF THE INVENTION

This is a continuation-in-part of application Ser. No. 534,510 filed inthe U.S. Patent and Trademark Office on Sept. 21, 1983, whose disclosureis incorporated hereby by reference.

The present invention is concerned with decoding in random accessmemories and in particular is concerned with a 64K memory.

An object of the invention is to provide an improved arrangement fordecoding addresses.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a RAM where the invention can be used.

FIG. 2 shows the final stages of multistage decoding according to thepresent invention.

FIG. 3 shows a first stage of multistage decoding.

FIG. 4 shows a ciruit implementation of logic gates of FIG. 2.

DETAILED DESCRIPTION

The unique multi-stage decoding is illustrated in FIGS. 2, 3, and 4. Itwill be noted that each stage in FIG. 2 has only two inputs. Thisgreatly improves the speed and the layout. As shown in FIG. 2, on theleft there are nine lines, eight of which represent logical combinationsfor row addresses A₀ through A₃. On the right side, there are 8 linesfor the rows A₄ through A₇. The ninth lines on the left and right aremarked A15 and A₁₅. The sixteen partially decoded row addresses areinputs from earlier stages. In FIG. 2, the first stage of decoding is aNAND gate 100 which receives signals from two of the predecoded rowaddress lines. This is applied to the second stages which consist of twoNOR gates 102. These each receive a second input from adjacent firststage decoders, and provide an output to the final stage 104 ofdecoding. Stage 104 selects whether the left half or the right half willbe used. Its output is applied to a buffer inverter 106.

More particularly, the row address bits are received by logic circuitrysimilar to that shown in FIG. 3. A_(n) and A_(n+1) inputs on lines 110and 112 represent paired row address bits, such as A₀ and A₁. These twobits are then processed through the various inverters and NAND gates asillustrated to develop four outputs A_(n).A_(n+1), A_(n).A_(n+1),A_(n).A_(n+1) and A_(n).A_(n+1) on lines 114, 116, 118 and 120,respectively. These outputs represent the result of a first stage ofdecoding of the paired row address bits A_(n) and A_(n+1).

In a system utilizing an eight bit (A₀ -A₇) row address signal, fourcircuits such as shown in FIG. 3 would be used to provide a total ofsixteen partially decoded row address signals for further processing.That is, A₀ and A₁ would be logically processed in one such circuit toprovide four outputs representative of A₀. A₁, A₀.A₁, A₀.A₁, and A₀.A₁on lines 114, 116, 118 and 120 respectively. Similarly, row address bitsA₂ and A₃, A₄ and A₅ and A₆ and A₇ would be combined in other suchcircuits to each provide four further outputs on the appropriate linesfor a total of sixteen partially decoded row address signals.

It is these sixteen partially decoded row address signals which provideinputs to the representational decoding circuitry of FIG. 2. The four A₀A₁ combination signals and the four A₂ A₃ combination signals arereceived at the left of FIG. 2 on the lines labelled "Predecoded RowAddress A₀ →A₃." Similarly, the four A₄ A₅ combination signals and thefour A₆ A₇ combination signals are received at the right of FIG. 2 onthe lines labelled "Predecoded Row Address A₄ →A₇."

The circuitry of FIG. 2 provides the final stages of the multistagedecoding of the present invention. Left and right NAND gates 100 eachreceive two partially decoded inputs for further decoding. Left NANDgate 100 receives one A₀ A₁ combination signal as one input and one A₂A₃ combination signal as its other input. Right NAND gate 100 receivesone A₄ A₅ combination signal as one input and one A₆ A₇ combinationsignal as its other input. The outputs of left and right NAND gates 100are further decoded through upper NOR gate 102 to drive row line 122high or low, depending on whether it is the "addressed" row or not.

In this fashion, an eight bit row address signal is decoded throughthree stages (stage one in the logic circuitry of FIG. 3, stage two atNAND gate 100, and stage three at NOR gate 102) to excite the desiredrow address line, e.g., line 122. The use of this multistage decodingtechnique allows each stage to be optimized for the greatest possibleoperational speed. Because of the selective optimization of theindividual stages, the multistage decoding technique of the presentinvention provides a faster chip access time than conventional methodswhich typically utilize a single-stage, eight-input decoding gate foreach row line.

A further selection process is performed by left and right NAND gates104 to decide whether X_(n) left or right is to be excited. Row line 122serves as one input to each NAND gate 104 with A₁₅ being the other inputto left NAND gate 104 and A₁₅ being the other input to right NAND gate104. Because A₁₅ and A₁₅ are logical opposites, only one of NAND gates104 will be activated. The output of the activated NAND gate 104 is thenbuffered by a buffer gate 106 to excite the appropriate X_(n).

In this final selection stage, the signal A₁₅ is used to select on whichside of the cell matrix the row line is to be excited. In the preferredembodiment, A₁₅ is the most significant bit of the eight bit columnaddress signal. Accordingly, A₁₅ will be "high" only when the second(right) half of the cell matrix is being addressed. When this occurs,X_(n) (right) will be excited. Otherwise, A₁₅ will be "low" (A₁₅"high"), and X_(n) (left) will be excited. In this fashion, powerconsumption is reduced because only that half of the matrix which isbeing addressed is "powered up." In the preferred embodiment, A₁₅indicates which side of the matrix is being addressed (and thus,"powered up"), and correspondingly excites the desired row line solelyon that side of the cell matrix by means of NAND gates 104. Of course,any signal indicative of the half of the cell matrix being addressedcould be used in the place of illustrative signal A₁₅.

In a system having an eight bit row address signal, there will be 256row address lines such as lines 122, 124, 126 and 130 illustrated inFIG. 2. NAND gates 100 and NOR gates 102 are accordingly laid out on thechip architecture to allow adjacent decoders to be shared asillustrated. For example, the particular A₄ A₅ and A₆ A₇ combinationdecoded by right NAND gate 100 is sent via line 130 to the next adjacentdecoder for final stage decoding with a decoded signal from a differentA₀ A₁ and A₂ A₃ combination than it was originally processed withinupper NOR gate 102. Similarly, lower NOR gate 102 receives as one of itsinputs the decoded output of a different A₄ A₅ and A₆ A₇ combinationfrom the next lower decoder. It will be understood that X_(N+1) isadjacent to X_(N) in the sense that X_(N+1) is physically next to X_(N)on the chip. These two lines are not necessarily next to each other in amathematical sense.

FIG. 4 illustrates a schematic representation of one embodiment of aCMOS implementation of the logic circuitry of FIG. 2 with thecorresponding gates bearing like reference numerals.

We claim:
 1. In a semiconductor memory device having inputs coupled forreceiving coded column and row address data, an improved row decodercomprising:a set of predecoding row address circuits having inputscoupled for receiving row address data and providing a set of predecodedrow address data; a pair of first stage row decoders each having twoinputs coupled to receive two respective predetermined ones of saidpredecoded row address data and providing respective first logic signalsat respective outputs of said first stage decoders; a second stage rowdecoder having two inputs coupled to receive said first logic signalsand to provide a second logic signal at an output of said second stagedecoder; and a pair of third stage decoders each having two inputs andeach having one of said inputs coupled to receive said second logicsignal and each having its other input coupled to receive column addressdata.
 2. In a semiconductor memory device having inputs coupled forreceiving coded column and row address data, an improved row decodercomprising:a set of predecoding row address circuits having inputscoupled for receiving row address data and providing a set of predecodedrow address data; a set of first stage row decoders each having twoinputs coupled to receive two respective predetermined ones of saidpredecoded row address data and providing respective first logic signalsat respective outputs of said first stage decoders; a set of secondstage row decoders each having two inputs coupled to receive tworespective first logic signals from adjacent first stage row decodersand to provide respective second logic signals at respective outputs ofsaid second stage decoders; a set of third stage decoders arranged inpairs, each decoder having two inputs, each of the decoders of each pairhaving one of said inputs coupled to receive a respective second logicsignal and each said decoder having its other input coupled to receivecolumn address data.
 3. The decoder of claim 1 wherein each of saidfirst stage, second stage and third stage decoders comprises arespective logic circuit coupled to receive two logic input signals andto provide one logic output signal.
 4. The decoder of claim 2 whereineach of said first stage, second stage and third stage decoderscomprises a respective logic circuit coupled to receive two logic inputsignals and to provide one logic output signal.
 5. The decoder of claim2 wherein a first logic stage decoder provides an output which iscoupled to the inputs of two second stage row decoders each havingrespective outputs coupled to four third stage decoders.
 6. The decoderaccording to claim 2 wherein a first group of said third stage decodersincludes decoders each having an input coupled to receive a singlecolumn address bit, and a second group of decoders each having an inputcoupled to the logic complement of said column address bit.
 7. Thedecoder according to claim 6 wherein said first group is coupled toreceive the most significant column address bit and said second group iscoupled to receive the logic complement of said most significant columnaddress bit.